O que é cascade inputs comparador de magnitude

Why the Cascading inputs has always to be (A>b ,0) (A<b, 0) (A=b , 1 ),, can sm 1 explain pls. thx

When you assemble several of these as a multiple-digit comparator, you cascade the < out to the < input of the next stage, = to = and > to >. This way, if the MSD (most significant digit) of A is greater than B, it will force the final output to A>B regardless of what the comparisons of the other digits are. All else being equal (a pun, yes, but if all other digits above the LSD are equal to each other), then the final output will be determined by the LSD. Rereading the original question, let me then add: A>B, A<B and A=B are all exclusive conditions. One and only one can be true, correct? So at the initial input, we make A=B as the true (1) input while the other two inputs are false (0). This puts the beginning of the comparision on an "equal" footing so to speak. The final output is based upon the digits being compared and not the original input.

These comparators are a lot of fun to work with. I made a digital frequency control for a function generator with a set of them. A keyboard enters the desired frequency into one set of comparator inputs, the output of a counter from the generator is fed to the other set of comparator inputs. The outputs of the comparator go to indicator lamps (to show the status of the control) and to + and - voltage sources that feed a charging capacitor and buffer amplifier which then feeds the VCO input of the functions generator. It's really neat to watch it operate!

Because the comparing inputs can dominate/override the cascaded inputs, not vice versa. That means the MSB which should be dominant during comparison must be compared in the last stage prior to output in order to actually be dominant.

Also, even if the IC was constructed so cascaded inputs override compare inputs, your way is less efficient. It's already more efficient this way. The output stage can act directly on the dominant MSB and can ignore the LSBs if they won't make a difference. Your way, the dominating MSB comparison result must cascade all the way through the LSB comparison ICs to get to the output.

Graphically, it might look like MSB is compared last because it is on the right, but that' just drawn so input to output moves from left to right. In actuality, the numerical bits get fed to all ICs at the same time and the cascade lags behind that. So all numerical bits are being compared at the same time and the MSB comparison can act the quickest since it can ignore the cascading LSB results to get the output out the door.

O que é cascade inputs comparador de magnitude

NXP 74HC85 Datasheet

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